This invention relates to semiconductor non-volatile memory devices, and more particularly to a dual-bit source-side injection cell which has two floating gates for storing two bits of information.,
There are two types of hot-electron injection flash EEPROM cells, classified by the location of the charge injection in the programming mode. They are commonly referred to as xe2x80x9cdrain-sidexe2x80x9d and xe2x80x9csource-sidexe2x80x9d injection cells. In a drain-side injection cell, electrons are injected onto the floating gate from a region in the source-drain channel near the drain junction; while in a source-side injection cell, electrons are injected onto the floating gate from a region in the source-drain channel near the source junction.
Source-side injection cell has superior programming characteristics because it requires substantially lower programming current than the drain-side injection cell. Therefore, source-side injection cells are more suitable for low power and low voltage applications.
FIGS. 1A and 1B are cross-section views of two types of source-side injection cells. FIG. 1A shows a triple-polysilicon source-side injection cell 100 disclosed in the U.S. Pat. No. 5,280,446 by Ma et al., incorporated herein by reference. FIG. 1B shows a double-polysilicon cell 150 disclosed in U.S. Pat. No. 5,029,130 by Yeh, incorporated herein by reference. A common feature of the cell structures 100 and 150 is that the channel between the source and drain junctions is covered partly by a floating gate and partly by a select-gate. Such structures are commonly referred to as a split-gate structure.
A structural difference between cells 100 and 150 is that the triple-polysilicon cell 100 has five operating terminals (select-gate 101, control-gate 102, drain 104, source 105, and substrate 106), while the double-polysilicon cell 150 has four operating terminals (select-gate 151, drain 154, source 155, and substrate 156). Note that drain junction 154 is deeper than source junction 155 to increase floating gate 153 to drain 154 overlap capacitance for improved voltage coupling from the drain to the floating gate. Cell 100 has a channel portion 109.
While the programming mechanisms of cell structures 100 and 150 are similar (e.g., source-side injection, shown by the arrows P in FIGS. 1A and 1B), their erase operations differ. In the triple-polysilicon cell 100, during erase, the electrons are tunneled from floating gate 103 to drain 104 via a thin gate-dielectric 107. This is shown by the arrow E in FIG. 1A. However, in the double-polysilicon cell 150, the electrons are tunneled from floating gate 153 to select-gate 151 via a thin inter-polysilicon dielectric 158 at a pointed corner of the floating gate 153. This is shown by the arrow E in FIG. 1B.
The manufacturing process for the double-polysilicon cell 150 is less costly and has a shorter fabrication cycle time than the triple-polysilicon cell 100, because cell 150 requires one less polysilicon by layer and thus fewer masking steps. However, the definition of sharp process development associated with the and the delicate inter-polysilicon dielectric 153 of cell 150 is quite tedious.
An important factor that directly impacts the cell-size and the array-size is the choice of array architecture. In conventional arrays, one bit-line contact is normally required for every two cells. In such xe2x80x9cdirect contactxe2x80x9d arrays, the bit-line contact occupies a substantial portion of the cell area. In an alternative xe2x80x9cvirtual groundxe2x80x9d (or so-called xe2x80x9ccontactlessxe2x80x9d) array approach, the number of contacts per cell is greatly reduced (typically by a factor of about 10xc3x97), hence resulting in smaller cell-size and smaller array-size. However, because of its inherently high bit-line resistance, the virtual-ground array suffers from slower memory access speed.
Memory cells 100 and 150 are single-bit cells (i.e., there is one floating gate in each cell for storing one bit of information). FIG. 2 is a cross-sectional view of a dual-bit triple-polysilicon cell structure 200 disclosed in U.S. Pat. No. 5,278,439 by Ma et al., incorporated herein by reference. Cell structure 200 is a six-terminal cell (select-gate 201, control-gates 202A and 202B, xe2x80x9cdrain/sourcexe2x80x9d junctions 204 and 205, and substrate 206) with two floating gates 203A and 203B. Each floating gate 203A, 203B stores one bit of information. Structurally, cell 200 is obtained by merging two adjacent mirror-facing single-bit cells of the kind in FIG. 1A so that the source junctions (i.e., source junction 105 in FIG. 1A) and a select-gate portion (corresponding to channel portion 109 in FIG. 1A) of the merged cells are eliminated. This results in a smaller cell-size per bit. Junctions 204 and 205 are interchangeable in their functions (as a source or a drain) depending on whether the right bit (e.g., information stored in floating gate 203A) or the left bit (e.g., information stored in floating gate 203B) is accessed. Control-gates 202A and 202B are reciprocally identical.
A drawback of cell 200 is that it has a longer effective channel-length than the single-bit cell 100. This results in higher channel resistance and thus a lower read-current in the cell. The lower read-current generally results in slower memory access time. Thus, the small cell-size and lower read-current of cell 200 makes this cell suitable for high density memory applications which generally have less stringent memory access time requirements.
With memory density and the access speed as the criteria, flash memory applications are generally divided into two commodity categories: (1) for code storage applications in which data access speed has greater importance than memory density, and (2) for mass-storage (or data storage) applications in which memory density has much greater importance than the access speed. Despite the small size of the dual-bit cell 200, its costly triple-polysilicon manufacturing process and complicated six-terminal operations, make it an unattractive option for the cost sensitive high density applications.
The NAND-type flash memory cell approach has become popular for mass-storage applications because of its small cell-size and its relatively simple double-polysilicon process. However, because its operation requires high voltage in both positive and negative polarities, designing the array decoders to fit within the tight cell-pitch limits future advancement of this technology. Also, because of its small read-current, the NAND-type array is more susceptible to noise immunity and suffers from slow sensing speed, and thus presents a greater challenge in achieving the target operation margins as technology scaling continues.
Thus, a new dual-bit cell with a comparable per bit cell-size to that of the NAND-type array but with higher read-current and fewer operating terminals, and which requires a simple process is needed for such applications as mass-storage.
In accordance with the present invention, a double-polysilicon cell structure is capable of storing two bits of information. In one embodiment, the cell structure includes a first junction and a second junction separated by a channel region, the first and second junctions being in a body region. A first and a second floating gates extend over the channel region. A select-gate has a portion located between the two floating gates, and the select-gate extends over at least a portion of each of the two floating gates.
In another embodiment, the first floating gate extends over a first portion of the channel region and over a portion of the first junction, and the second floating gate extends over a second portion of the channel region and over a portion of the second junction.
In another embodiment, each of the first and second floating gates has at least one slanted surface forming a sharp edge.
In another embodiment, an inter-polysilicon dielectric layer insulating the first and second floating gates from the select-gate is thinnest between the sharp edge of each of the two floating gates and the select-gate.
In another embodiment, the portion of the select-gate between the two floating gates extends over a third portion of the channel region between the first and second channel portions, wherein the first, second, and third portions of the channel region do not overlap with one another, and the first, second, and third channel portions together form the entire channel region between the first and second junctions.
In another embodiment by applying a first positive voltage to the first junction and a second positive voltage to the select-gate and grounding the second junction and the body region a potential on the first floating gate is decreased through hot-carrier injection mechanism.
In another embodiment, by applying a positive voltage to the select-gate and grounding the first junction, the second junction, and the body region a potential of the first floating gate and a potential of the second floating gate are simultaneously increased through tunneling mechanism.
In another embodiment, the amount of charge on the first floating gate is detected by applying a first positive voltage to the select-gate, a second positive voltage to the second junction and grounding the first junction and the body region.
In another embodiment, the amount of charge on the first floating gate is detected by applying a first positive voltage to the select-gate, a second positive voltage to the second junction, a third positive voltage to the first junction, and grounding the body region, wherein the second positive voltage is greater than the third positive voltage.
In another embodiment, the amount of charge on the first floating gate is detected by applying a first positive voltage to the select-gate, a second positive voltage to the second junction, and measuring the voltage at the first junction while forcing a predetermined amount of current through the channel region.
In another embodiment, the body region is a first well of a first conductivity type, the first well being formed in a second well of a second conductivity type opposite the first conductivity type, the second well being formed in a substrate region of the first conductivity type, wherein the first and second junctions are of the second conductivity type. The first well is capable of being independently biased to a predetermined positive or negative or zero voltage.
In another embodiment, the at least one slanted surface of each of the first and second floating gates is either a side surface or a top surface of each of the first and second floating gates.
In another embodiment, two opposing side surfaces of each of the two floating gates are slanted forming two sharp edges.
In another embodiment, a top surface of each of the first and second floating gates is bowl-shaped forming two sharp edges.
In another embodiment, two opposing side surfaces of each of the two floating gates are slanted and a top surface of each of the two floating gates is bowl-shaped, the combination of the two slanted side surfaces and the bowl-shaped top surface forming two sharp edges.
In another embodiment, the cell structure in combination with other similar cell structures forms a virtual ground array, wherein the cells are serially connected along a plurality of rows and columns. The select-gates of the cells along each row are connected together forming a wordline. The first junctions of cells along each column are connected together forming a continuous bitline, and the second junctions of the cells along each column are connected together forming another continuous bitline.
In accordance with another embodiment of the present invention, a method of forming the memory cell includes: forming a first junction and a second junction in a body region, the first and second junctions being separated by a channel region; forming a first floating gate and a second floating gate over the channel region, each of the first and second floating gates having at least one slanted surface forming a sharp edge; and forming a select-gate over at least a portion of each of the first and second floating gates, the select-gate having a portion between the first and second floating gates.
In another embodiment, the method includes: forming an inter-polysilicon dielectric layer for insulating the first and second floating gates from the select-gate, the inter-polysilicon dielectric layer being thinnest between the sharp edge of each of the two floating gates and the select-gate; forming an insulating layer for insulating the first and second floating gates from their underlying channel regions; and forming an insulating layer for insulating the select-gate from its underlying channel region.
Other features and advantages of the invention are described below. The invention is defined by the appended claims.